EMRFD Message Archive 6761
Message Date From Subject 6761 2011-10-27 14:47:24 jasonb1963 Thoughts on 15M Transceiver?
All of the individual pieces in this design are adaptations of work done by others. The only thing that may be unique about it is the way I've (mis)combined the pieces.
The VFO is logic gate from a 74HC240 operating as a Colpitts oscillator and utilizing a varactor diode to tune across about 200kHz of bandwidth. More bandwidth is easily achievable, but I'm not sure it's advisable. The output is buffered by another gate on the 74HC240, and inverted by a third gate since the mixer needs to 180-degree out-of-phase signals to drive it.
The receiver is direct conversion and is based on a 74HC4066 operating as a switch. The mixer operates at 7MHz (doesn't work above about 10MHz), so the 3rd harmonic of the 7MHz is used, giving about a 10dB loss vs. a signal on the fundamental. The front end consists of a 21MHz bandpass filter and a J310 preamplifier operating in common gate mode in an attempt to limit the amount of VFO signal getting to the antenna and to reduce microphonics by reducing the amount of audio gain needed. The pre-amp is only providing about 6dB of gain, which seems on the low side. I may need to increase the turns ratio on the transformer to up this to 10dB. Following the mixer, a dual op-amp provides up to about 45dB of gain, and then an active low pass filter which also provides another 6dB of gain. I'm thinking of switching to a quad op-amp and using two sections for more gain, and two sections to make a sharper low pass filter. I haven't made any IIP3 measurements yet (need to make a hybrid combiner), but I did measure the MDS by ear and it was a rather disappointing -110dBm (BW was about 2KHz -- need to reduce this for CW work).
The T/R switching is right out of EMRFD. Your basic series-tuned LC filter with some limiting diodes in between. I'm unsure about interaction with the low pass output filter and/or the bandpass filter before the preamplifier. This is the only portion of the circuit I have not built and tested and I would appreciate any advice or suggestions here. It also switches the receive portion of the circuitry on and off with the remaining gate in the 74HC240 in order to mute the receiver while transmitting. I may need to put in a PNP switching transistor here, but so far the current draw is well below the 35mA rating on the 74HC240.
The transmitter uses the second half of the 74HC240. The first gate buffers the VFO and drives a 21MHz bandpass filter. The second gate amplifies (squares) the output and drives the remaining two gates which are operated in parallel. Output power available into 50 ohms is about 50mW at this point (at 6V).
I think 50mW is too low, even for 15M QRP, so I want to add a modest power amplifier to the transceiver to bump it up something over 1 watt. I have gotten class E amplifiers working with BS170s up through 20M, where the efficiency starts dropping. I'm not sure it would offer anything over a good class C amplifier on 15M, and I don't want to use any RF mosfets (too expensive). I have been wondering why BJTs are not more widely used as class E amplifiers? I've replaced the BS170 in some class E designs with 2N2222A's (VCEO=40V) and after re-tuning gotten reasonable performance out of them (maybe 75% vs. 85% efficiency on 40M). The square wave output drive from the 74HC240 is ideal for this mode.
A couple more modifications I'm considering. I could replace the 74HC4066 with a 74CBT3125 and run the VFO at 21MHZ. This will recover around 10dB of mixer loss, and double the output to around +20dBm. It does force me to use a surface mount part, at which point I may as well have a PCB made and go 100% surface mount.
So long as we're talking surface mount, I could add a $3 CPLD and use it to create a digital frequency display with some generic 7-segment LEDss. If there are enough gates left over support for an iambic keyer could be included as well.
I have a fairly up-to-date set of schematics available at http://dl.dropbox.com/u/17650857/15M_CMOS_TRX.pdf
--
Jason6762 2011-11-01 09:03:47 Tim Re: Thoughts on 15M Transceiver?
That doesn't mean I haven't made contacts with them. I got a lot of postcards from many OO's across the country while I was using my HG-10B VFO on 15M and 10M a couple years back :-). (If you want to hear my HG-10B and HW-16 on the air, Straight Key Night on 80M is sure when they'll get activated. The chirp and whoop aren't nearly so bad on 80M and usually elicit compliments rather than OO postcards there!)
My homebrew efforts for direct or multiplied-up LC VFO applications6763 2011-11-03 13:59:00 jasonb1963 Re: Thoughts on 15M Transceiver?
Thanks for the reply. You make a good point about the problems of oscillator stability at 15M. I originally set this up to work6764 2011-11-04 06:51:16 Harold Smith Re: Thoughts on 15M Transceiver?
the bottom 100 kHz or so. I have built and tested a variable oscillator
that runs at 18.05 MHz, and tunes down to 18.005. Doubled to 36.1 and used
with an 8 MHz IF, I'll have almost precisely the frequency range I'm
looking for. Stability at 36 MHz is *+* about 5 Hz. The circuit is a
Super VXO, basically a Colpitts crystal oscillator, but with a pair of
crystals (same nominal frequency) and a network consisting of an inductor
(in this case a 6.8 uH molded choke) and a 140 pF variable cap in series
with the crystals.
The Super VXO is a simple circuit, though it can take some tweaking to get
it working the way you want, which is why it's pretty much never used
commercially. But it's an excellent bet for a one-off homebrew radio. In
fact, the biggest catch is that you need crystals at the right frequency.
(The ones I'm using in the 10m radio are surplus, nominally 54.2 MHz 3rd
overtone, but used in this case on their fundamental.)
It's cheaper than any of the SI570 or synthesized approaches, much more
stable than an LC VFO, and cleaner than a heterodyne approach. Take a
couple of hours and try it, and see if it might not work for you. Assuming
you can get the frequency you need, of course. If not, it's still worth
keeping in mind for another project.
de KE6TI, Harold
6766 2011-11-04 11:46:06 jeffthom99 Re: Thoughts on 15M Transceiver? 6767 2011-11-04 12:32:47 John Kolb Re: Thoughts on 15M Transceiver?
to time, as recently
as yesterday when someone complained about one that measured only the VFO freq
rather than also measuring the down conversion xtal oscillators
involved in the process.
Main drawback is finding a circuit board to put the CPLD on for
prototyping. Too many
small pins for dead bug construction. I liked CPLDs better when they
ran6768 2011-11-04 17:55:24 jasonb1963 Re: Thoughts on 15M Transceiver?
Thanks for the excellent suggestion. I have in fact played with the multi-crystal VXOs some time ago when I first came across the circuit in EMRFD. However, at the time I was not thinking of their application on the higher bands and found I could not get more than about 15KHZ of tuning range at 40M (with both inductor + varicap). That would translate to about 45KHz of tuning range at 15M, or 60KHz at 10M, so you are doing considerably better than I was. Still, that's enough range for most CW work.
Another related approach I have also played with is using ceramic resonators rather than crystals for a VXO. These easily give 200KHz of tuning range around 40M, but it was impossible to find the right frequencies for use in the amateur bands, to my disdain.
Anyway, I will look around in my crystal collection to see if I have anything suitable for use6769 2011-11-04 18:38:10 jasonb1963 CPLD Frequency Counter
Happy to start a thread on the frequency counter.
I am using the Xilinx XC9572XL CPLD in the 44-pin package and the -10 (slowest) variant. It is Digikey part number 122-1448-ND and currently priced at $2.26.
The XC9500 series of CPLDs run on 3.3 volts, but are 5V tolerant so you can drive them with 5V levels, and they will drive 5V parts as well, although with reduced noise margin.
In low power mode, the current consumption is on the order of 30mA, so that's probably not what you were hoping for and not less than a number of microcontrollers.
On the plus side, the above-referenced part will count up to nearly 100MHz (though that may push up the power consumption) before under-counting. I haven't run into many 8-bit or 16-bit microcontrollers that can do more than about 10% of this (Atmel and Microchip products specifically). In general, microcontrollers with built-in counters are limited to a maximum count frequency of less than 1/2 the clock rate, so you need an external prescaler if you want to go above around 10MHz or so and then you lose resolution.
Now it turns out that for lowest power use, there is a better CPLD to use than the XC9500 series. It's the newer "Coolrunner II" CPLDs from Xilinx. These have 1.8V cores instead of 3.3V cores and with an equivalent number of logic elements to the XC9572XL consume on the order of 5mA (six times less than the XC9572XL). They are also slightly faster than the XC9500 series. The only downside is that they are not 5V compatible -- they only go up to 3.3V logic levels on the I/O lines. Still, this probably makes the most sense where power consumption is critical and I will ultimately switch over to this series myself. Take a look at Digikey part number 122-1418-ND for an example.
Now getting to the architecture of the frequency counter itself. It's really nothing more than an external oscillator (I used 1MHz, but any frequency which is evenly divisible by the minimum frequency resolution you want will work) plus the CPLD.
You divide the reference oscillator frequency down to the minimum resolution you want for your frequency counter. Bear in mind that there is a tradeoff between how often the counter updates its count and your minimum resolution. You will get Fmin counts per second. If you are multiplexing 5 or 6 displays as I was, I found that a 100Hz resolution produced too much flicker, so if you need 100Hz or better resolution and a display, you should probably go ahead and take advantage of the large number of I/O lines on the CPLD to drive each display separately.
The CPLD can be programmed in a number of languages, but the most popular are VHDL and Verilog. Both are roughly equal in popularity, although VHDL seems somewhat more popular in universities, so that is what I chose to start with myself.
Let me prepare the VHDL I have by cleaning up my comments a bit and I will post it here in the next day for all to see. For those of you who do this stuff for a living, please be gentle as this was basically the first HDL program I wrote myself. I hope to be able to comment it such that anyone with some programming experience will be able to see how it works and then modify it to suit their own needs.
Aside from making a handy inexpensive display (low power if you use the Coolrunner II CPLD family, too), another application I'd like to try is to combine the display with some additional logic to drive a frequency-locked-loop (huff-puff). It will no doubt require a bit of analog circuitry (perhaps no more than a low pass filter to drive a varactor in the VFO circuitry), but it may have the potential to stabilize a high-performance LC oscillator and enable operation at somewhat higher frequencies than they are normally used. Certainly if the rate of drift is significantly below 1Hz/s, then it would seem that the possibility of stabilizing to +/- 1Hz is present.
If you find this technology as interesting as I do, one place you can pick up an inexpensive ($15) "breakout" board for a CPLD is http://www.seeedstudio.com/depot/xc9572xl-cpld-development-board-p-799.html?cPath=174 (5V compatible, but higher power version) or http://www.seeedstudio.com/depot/xc2c64a-coolrunnerii-cpld-development-board-p-800.html?cPath=174 (low power, but 3.3V limit). Bear in mind that you will need some kind of JTAG programmer in order to program these. Xilinx offers free software (ISE webpack) for programming these devices which you can download from their web site -- though it is only compatible with Xilinx JTAG programmers (cheaper clones are available -- try eBay). Tutorials are available to get you started writing your first HDL program and uploading it to the CPLD. I have no affiliati6770 2011-11-04 19:07:01 Ashhar Farhan Re: CPLD Frequency Counter
Some links on getting started with cplds?
I have also wondered if one could detect if the huff n puff should
push th freq up or down by using a phase-frequency detector instead of
just a modulo-n counter.
- farhan VU2ESE
On 11/5/11, jasonb1963 <jasonb1963@yahoo.com> wrote:
> Hi Jeff,
>
> Happy to start a thread on the frequency counter.
>
> I am using the Xilinx XC9572XL CPLD in the 44-pin package and the -10
> (slowest) variant. It is Digikey part number 122-1448-ND and currently
> priced at $2.26.
>
> The XC9500 series of CPLDs run on 3.3 volts, but are 5V tolerant so you can
> drive them with 5V levels, and they will drive 5V parts as well, although
> with reduced noise margin.
>
> In low power mode, the current consumption is on the order of 30mA, so
> that's probably not what you were hoping for and not less than a number of
> microcontrollers.
>
> On the plus side, the above-referenced part will count up to nearly 100MHz
> (though that may push up the power consumption) before under-counting. I
> haven't run into many 8-bit or 16-bit microcontrollers that can do more than
> about 10% of this (Atmel and Microchip products specifically). In general,
> microcontrollers with built-in counters are limited to a maximum count
> frequency of less than 1/2 the clock rate, so you need an external prescaler
> if you want to go above around 10MHz or so and then you lose resolution.
>
> Now it turns out that for lowest power use, there is a better CPLD to use
> than the XC9500 series. It's the newer "Coolrunner II" CPLDs from Xilinx.
> These have 1.8V cores instead of 3.3V cores and with an equivalent number of
> logic elements to the XC9572XL consume on the order of 5mA (six times less
> than the XC9572XL). They are also slightly faster than the XC9500 series.
> The only downside is that they are not 5V compatible -- they only go up to
> 3.3V logic levels on the I/O lines. Still, this probably makes the most
> sense where power consumption is critical and I will ultimately switch over
> to this series myself. Take a look at Digikey part number 122-1418-ND for
> an example.
>
> Now getting to the architecture of the frequency counter itself. It's
> really nothing more than an external oscillator (I used 1MHz, but any
> frequency which is evenly divisible by the minimum frequency resolution you
> want will work) plus the CPLD.
>
> You divide the reference oscillator frequency down to the minimum resolution
> you want for your frequency counter. Bear in mind that there is a tradeoff
> between how often the counter updates its count and your minimum resolution.
> You will get Fmin counts per second. If you are multiplexing 5 or 6
> displays as I was, I found that a 100Hz resolution produced too much
> flicker, so if you need 100Hz or better resolution and a display, you should
> probably go ahead and take advantage of the large number of I/O lines on the
> CPLD to drive each display separately.
>
> The CPLD can be programmed in a number of languages, but the most popular
> are VHDL and Verilog. Both are roughly equal in popularity, although VHDL
> seems somewhat more popular in universities, so that is what I chose to
> start with myself.
>
> Let me prepare the VHDL I have by cleaning up my comments a bit and I will
> post it here in the next day for all to see. For those of you who do this
> stuff for a living, please be gentle as this was basically the first HDL
> program I wrote myself. I hope to be able to comment it such that anyone
> with some programming experience will be able to see how it works and then
> modify it to suit their own needs.
>
> Aside from making a handy inexpensive display (low power if you use the
> Coolrunner II CPLD family, too), another application I'd like to try is to
> combine the display with some additional logic to drive a
> frequency-locked-loop (huff-puff). It will no doubt require a bit of analog
> circuitry (perhaps no more than a low pass filter to drive a varactor in the
> VFO circuitry), but it may have the potential to stabilize a
> high-performance LC oscillator and enable operation at somewhat higher
> frequencies than they are normally used. Certainly if the rate of drift is
> significantly below 1Hz/s, then it would seem that the possibility of
> stabilizing to +/- 1Hz is present.
>
> If you find this technology as interesting as I do, one place you can pick
> up an inexpensive ($15) "breakout" board for a CPLD is
> http://www.seeedstudio.com/depot/xc9572xl-cpld-development-board-p-799.html?cPath=174
> (5V compatible, but higher power version) or
> http://www.seeedstudio.com/depot/xc2c64a-coolrunnerii-cpld-development-board-p-800.html?cPath=174
> (low power, but 3.3V limit). Bear in mind that you will need some kind of
> JTAG programmer in order to program these. Xilinx offers free software (ISE
> webpack) for programming these devices which you can download from their web
> site -- though it is only compatible with Xilinx JTAG programmers (cheaper
> clones are available -- try eBay). Tutorials are available to get you
> started writing your first HDL program and uploading it to the CPLD. I have
> no affiliati6771 2011-11-05 00:30:22 John Kolb Re: CPLD Frequency Counter
huff n puff.
One could store the desired freq when first found, and get a
continuous error correction
signal rather than rolling over to the next modulo-n increment if the
drift goes too far.
John
KK6IL
At 06:06 PM 11/4/2011, you wrote:
>Jason,
>
>Some links on getting started with cplds?
>
>I have also wondered if one could detect if the huff n puff should
>push th freq up or down by using a phase-frequency detector instead of
>just a modulo-n counter.
>
>- farhan VU2ESE6774 2011-11-05 04:39:29 joop_l Re: CPLD Frequency Counter 6776 2011-11-05 08:44:25 drmail377 Re: CPLD Frequency Counter
I saw your CPLD frequency counter project on the Dangerous Prototypes Blog. Nice work.
How did you program your Xlinx CPLD. I have one each of the two different Dangerous Prototypes (DP) Xilinx CPLD breakouts bought from Seeed. Awhile back I did 'blink a LED' on one of the CPLD DP breakout boards using my Bus Pirate (again DP design bought via Seeed) with the JTAG-XSVF firmare loaded.
But this IMO is unacceptable. I need the Bus Pirate for other things, and blowing XSVF files to the target is less than ideal. Better to have a native programmer that works with the (bloated) Xilinx ISE WebPack dev system IMO.
I (foolishly) bought a Chinese Parallel Cable III (DLC-5) clone off ebaY (around twelve bucks). What a waste of money. There were hidden shipping costs - and after trying to reverse-engineer it (potted) it was mostly a passive device. It did not work.
So now I'm going to try building my own DLC-5 clone. Take a look at this link:
http://dev.ivanov.eu/index.php?page=dlc5-jtag
This design uses only one 74HC125 and should work with both 3.3V and 5.0V targets (I simulated it in LTSpice-IV).
Your thoughts?
73's, David WB4ONA
6778 2011-11-05 11:04:35 jeffthom99 Re: CPLD Frequency Counter 6779 2011-11-05 16:58:11 jasonb1963 Re: CPLD Frequency Counter
Here are a few that I have used:
http://www.dangerousprototypes.com -- these are the people who made the CPLD breakout board I used. There are some basic tutorials included there as well.
http://www.xilinx.com -- If you decide to use a Xilinx CPLD, you can download their free ISE Webpack from here. It's a complete IDE for developing applications using their CPLDs (and FPGAs). There are some limitations with the free version, but you most likely won't notice them for CPLD development. The software includes a simulator, so you don't even need to have a physical CPLD to get started.
http://www.altera.com -- Another manufacturer of CPLDs/FPGAs that offers free software for development on their products. Xilinx and Altera are the two big companies in this field, although there are a lot of smaller ones active as well (including Atmel for those of you who already have some experience with their products).
There are a number of books that sort-of cover the subject, but most of them emphasize FPGA development. Still, they are going to have a number of chapters of useful information. One which I own is _Rapid Prototyping of Digital Systems_ by J.O. Hamblen, T.S. Hall, and M.D. Furman. You can order it online from Barnes & Noble or Amazon. There are also other books which go into more detail on VHDL or Verilog programming -- and these may be more worthwhile once you've decided which of the two languages you prefer.
Finally, there is no reason why you couldn't implement an XOR-type phase detector with a CPLD, or even the more complex phase-frequency detector that uses a simple state machine. I suppose for HF frequencies, there is no reason why a CPLD combined with a VCO and a few passive components couldn't replace a low frequency PLL. This seems like it would be a nice approach for a DSP-based system with a reasonable bandwidth so that the step size limitations of a PLL system wouldn't matter much, but I don't think it is a good solution by itself for a CW or SSB rig.
I'm a little confused by what you mean by using a phase detector with the huff-n-puff circuit rather than a frequency counter. Seems to me you are talking about a PLL there, though possibly one that locks onto a manually tuned frequency instead of locking the VFO to a programmed frequency?
--
Jason
6780 2011-11-05 17:06:18 jasonb1963 Re: CPLD Frequency Counter
Yes, you are right. You could have a separate input signal by which the user would indicate that the present frequency was to be "locked". The CPLD could store this frequency, and then during each gating interval, compute a positive or negative difference and output a correcti6781 2011-11-05 17:25:16 jasonb1963 Re: CPLD Frequency Counter
I didn't realize the microchip parts had such a prescaler, but I see you are right. That must be one reason why they seem to be slightly more popular in the amateur community than the equivalent Atmel parts which I have used myself.
Now, reading the specs on the 12F629 you mention, I see that the prescaler is 8-bit programmable. So you could program it, for example, to divide the input by 10. I see how this would enable you to count much higher frequencies than the 10MHz limitation that would be present with the Atmel parts I've worked with (clocked at the maximum 20MHz).
Now, I understand that you can get 1Hz resolution or better by using a software counter6783 2011-11-05 18:13:36 jasonb1963 Re: CPLD Frequency Counter
I share your belief that there is a good partnership to be had by combining the advantages of microcontrollers and CPLDs. Even more so by just going straight to FPGAs, but I'm not quite there myself yet due to the learning curve and CPLDs seem like a perfect stepping stone.
I look forward to the day when we can go out in the field with a portable transceiver we've built ourselves and have a PSK (or other digital mode) QSO with another ham halfway around the world.
I've cleaned up the comments on the VHDL code and uploaded it to the
FILES section of the group. I look forward to any feedback anyone may have. I'm a relative beginner with VHDL so please don't assume the code is a parag6784 2011-11-05 21:32:07 Ashhar Farhan Re: CPLD Frequency Counter
Thanks for the links. I haven't kept up with the tools and
technologies of programmable devices since mead and conway.
When I do get some decent time on the bench I want to try using a
phase-frequency detector of some sort in an HnP so that instead of
oscilating the frequency on every pulse, it took care to see the
direction of the natural drift before correcting it. Probably a two
stage counter could do that as well.
These links will make for great weekend readings. Thanks.
- farhan VU2ESE
On 11/6/11, jasonb1963 <jasonb1963@yahoo.com> wrote:
> Hi Jeff,
>
> I share your belief that there is a good partnership to be had by combining
> the advantages of microcontrollers and CPLDs. Even more so by just going
> straight to FPGAs, but I'm not quite there myself yet due to the learning
> curve and CPLDs seem like a perfect stepping stone.
>
> I look forward to the day when we can go out in the field with a portable
> transceiver we've built ourselves and have a PSK (or other digital mode) QSO
> with another ham halfway around the world.
>
> I've cleaned up the comments on the VHDL code and uploaded it to the
> FILES section of the group. I look forward to any feedback anyone may have.
> I'm a relative beginner with VHDL so please don't assume the code is a
> parag6785 2011-11-07 01:59:12 joop_l Re: CPLD Frequency Counter 6789 2011-11-07 19:14:36 jasonb1963 Re: CPLD Frequency Counter