EMRFD Message Archive 6321
Message Date From Subject 6321 2011-05-17 20:23:44 rcbuckiii DDS driven PLL
Let's assume the DDS has a range of +/-5 KHz. Does that mean the PLL should have a step size of 5 KHz? And that you keep track of the DDS output and everytime it crosses a +/-5 barrier you step the PLL to the next step?
I was thinking of experimenting with the DDS-PLL combination. But I am not sure I really need to go to that trouble. If I am using a DDS clocked at 400 MHz (AD9951) and a local oscillator of 23 MHz will the spurs be down enough that I don't need the PLL to clean it up?
Ray
AB7HE6325 2011-05-18 06:53:05 kb1gmx Re: DDS driven PLL 6326 2011-05-18 09:18:10 rcbuckiii Re: DDS driven PLL 6327 2011-05-18 11:47:21 kb1gmx Re: DDS driven PLL 6329 2011-05-18 19:54:38 Graham / KE9H Re: DDS driven PLL 6330 2011-05-19 01:20:50 victor Re: DDS driven PLL
http://lea.hamradio.si/~s57nan/ham_radio/dds_9851/dds_9851.html
The DDS chip is used as a sophisticated fractional-N divider for the PLL.
Victor - 4Z4ME
6331 2011-05-19 05:51:02 Tim Re: DDS driven PLL 6337 2011-05-19 13:54:03 rcbuckiii Re: DDS driven PLL 6338 2011-05-19 14:56:13 kb1gmx Re: DDS driven PLL 6339 2011-05-19 16:51:07 rcbuckiii Re: DDS driven PLL 6341 2011-05-20 00:19:39 Nick Re: DDS driven PLL
although I am not an expert on the Hybrid DDS/PLL subject, it just happened to
study this design some months ago in order to understand the concept .
I will try to pass my understanding on the programming part , which comes directly form the way (I understood) the design works.
Besides the DDS, you also need a PLL chip. The PLL chip I assume it contains a phase detector, a reference frequency divider (usually called R counter) and a VFO frequency divider (usually called as N
counter).
Both counters are loaded with an integer divider (e.g 20 or 345 etc ).
The PLL will lock if the VFO frequency divided by the N counter, matches the reference frequency divided by the R counter. As the reference frequency we use the output of the DDS.
So, for example, if your VFO needs to cover the range 23-23.5 Mhz in steps of 10 hz , then one solution is the following (This is an example, and not the only or best solution ):
First, if your DDS chip is clocked at 400Mhz, with a 32bit tuning word it
means that the minimum frequency is can generate is Fclock/(2^32) which
is something around 0.0931 Hz.
The output frequency of the DDS is Fo = TuningWord * (Fclock/(2^32))
(this is
valid if your tuning word stays below 2^31). Thus the tuning word for a
given frequency is TuningWord = (Fdesired * (2^32)) / Fclock
Next, lets say that you divide the VFO by 230, so at 23 Mhz the divided VFO
frequency becomes 100 Khz. (this is the "step" of the PLL, see below)
In order for the PLL to lock , your DDS along with any division selected
by the value of the PLL R counter should result in a frequency of
100Khz.
Let's say that you select R counter to be 10. This means that you need
the DDS to produce a frequency of 1 Mhz. (do the math to find the DDS
tuning word).
If you need to move your VFO frequency to 23.000010 MHz , then you have to
alter the frequncy of the DDS only. By how much? the VFO of 23.000010
MHz is divided by 230 (N counter) which gives 100000.043478261 Hz . If you
multiply this by the R counter (10) you need from the DDS a frequency of 1000000.43478261 Hz ...do the math to obtain the new tuning word. This goes on until the VFO reaches the frequency of 23.099999 MHz. The DDS
frequency at this point will be 1004347.7826087 Khz . when you reach
23.100000 MHz you need to set the N counter to 231. You should leave the R
counter to 10. This means that the VFO of 23.100000 MHz is divided down to
100 Khz again, so the DDS has to start over again from 1 Mhz.
In the above example this means that the PLL gives the coarse tuning in
segments of 100Khz and the DDS does the fine tuning by generating the
intermediate frequencies. The DDS should produce frequencies between 1
Mhz and 1.0043477826087 Mhz. so you cover the required frequency range
like this:
R is set to 10,
N=230, DDS 1...1.0043477826087 Mhz => VFO 23.0-23.099999Mhz
N=231, DDS 1...1.0043477826087 Mhz => VFO 23.1-23.199999Mhz
N=232, DDS 1...1.0043477826087 Mhz => VFO 23.2-23.299999Mhz
N=233, DDS 1...1.0043477826087 Mhz => VFO 23.3-23.399999Mhz
N=234, DDS 1...1.0043477826087 Mhz => VFO 23.4-23.499999Mhz
The DDS frequency should always be (VFO/N) * R in order to get a PLL lock. Now that you have the values of R, N and DDS tuning word, you have to
consult the chipsets' datasheet
in order to program each one of them with the appropriate sequence of bytes
You also have to take into account a number of factors like:
a) the above calculations are performed with full precision but the DDS
uses integer only values, which means that the rounding of the tuning
word to the nearest integer value may result in a small frequency error
b) The exact frequnecies combination (which affects the choice of N and R
counter ) as well as the desicion of whether the PLL step should be
100Khz or 10Khz or 1Mhz belongs to the domain of PLL design
c) You have to
check which is the best DDS frequency range to use to minimize the DDS
spurs (you ahould carefully read the chipset datashhet and you can also
use the online tool from Analog Devices http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx) .
You should generally stick below Fclock/3 and select a region that does not contain a lot of spurs or images.
I hope this helps you to understand the part of managing the DDS and PLL
counters. As far as the PLL design specifics are concerned, I am
afraid I am not the right pers6342 2011-05-20 00:31:17 Nick Re: DDS driven PLL
Hi Ray and group,
although I am not an expert on the Hybrid DDS/PLL subject, it just happened to study this design some months ago in order to understand the concept .
I will try to pass my understanding on the programming part , which comes directly form the way (I understood) the design works.
Besides the DDS, you also need a PLL chip. The PLL chip I assume it contains a phase detector, a reference frequency divider (usually called R counter) and a VFO frequency divider (usually called as N counter). Both counters are loaded with an integer divider (e.g 20 or 345 etc ).
The PLL will lock if the VFO frequency divided by the N counter, matches the reference frequency divided by
the R counter. As the reference frequency we use the output of the DDS.
So, for example, if your VFO needs to cover the range 23-23.5 Mhz in steps of 10 hz , then one solution is the following (This is an example, and not the only or best solution )
First, if your DDS chip is clocked at 400Mhz, with a 32bit tuning word it means that the minimum frequency is can generate is Fclock/(2^32) which is something around 0.0931 Hz.The output frequency of the DDS is Fo = TuningWord * (Fclock/(2^32)) (this is valid if your tuning word stays below 2^31). Thus the tuning word for a given frequency is TuningWord = (Fdesired * (2^32)) / Fclock
Next, lets say that you divide the VFO by 230, so at 23 Mhz the divided VFO frequency becomes 100
Khz. (this is the "step" of the PLL, see below) In order for the PLL to lock , your DDS along with any division selected by the value of the PLL R counter should result in a frequency of 100Khz. Let's say that you select R counter to be 10. This means that you need the DDS to produce a frequency of 1 Mhz. (do the math to find the DDS tuning word).
If you need to move your VFO frequency to 23.000010 MHz , then you have to alter the frequncy of the DDS only. By how much? the VFO of 23.000010 MHz is divided by 230 (N counter) which gives 100000.043478261 Hz . If you multiply this by the R counter (10) you need from the DDS a frequency of 1000000.43478261 Hz ...do the math to obtain the new tuning word. This goes on until the VFO reaches the frequency of 23.099999 MHz. The DDS frequency at this point will be 1004347.7826087 Khz. when you reach 23.100000 MHz you need to set the N counter to 231. You should leave the R counter to
10. This means that the VFO of 23.100000 MHz is divided down to 100 Khz again, so the DDS has to start over again from 1 Mhz.
In the above example this means that the PLL gives the coarse tuning in segments of 100Khz and the DDS does the fine tuning by generating the intermediate frequencies. The DDS should produce frequencies between 1 Mhz and 1.0043477826087 Mhz. so you cover the required frequency range like this:
R is set to 10,
N=230, DDS 1...1.0043477826087 Mhz => VFO 23.0-23.099999 Mhz
N=231, DDS 1...1.0043477826087 Mhz => VFO 23.1-23.199999 Mhz
N=232, DDS 1...1.0043477826087 Mhz => VFO 23.2-23.299999 Mhz
N=233, DDS 1...1.0043477826087 Mhz => VFO 23.3-23.399999 Mhz
N=234, DDS 1...1.0043477826087 Mhz => VFO 23.4-23.499999 Mhz
The DDS frequency should always be (VFO/N) * R in order to get a PLL lock. Now that you have the values of R, N and DDS tuning word, you have to consult the chipsets'
datasheet in order to program each one of them with the appropriate sequence of bytes.
You also have to take into account a number of factors like:
a) the above calculations are performed with full precision but the DDS uses integer only values, which means that the rounding of the tuning word to the nearest integer value may result in a small frequency error
b) The exact frequnecies combination (which affects the choice of N and R counter ) as well as the desicion of whether the PLL step should be 100Khz or 10Khz or 1Mhz belongs to the domain of PLL design
c) You have to check which is the best DDS frequency range to use to minimize the DDS spurs (you ahould carefully read the chipset datashhet and you can also use the online tool from Analog Devices http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx) .
You should generally stick below Fclock/3 and select a region that does not contain a lot of spurs or
images.
I hope this helps you to understand the part of managing the DDS and PLL counters. As far as the PLL design specifics are concerned, I am afraid I am not the right pers6343 2011-05-20 01:54:03 Weddig, Henning-C... Re: DDS driven PLL
June
Building a Microwave
Frequency Synthesizer —
Part 1: Getting Started
By Alexander Chenakin
Phase Matrix, Inc.
to part 5 September
in the magazine highfrequencyelectronics of 2008:
http://www.highfrequencyelectronics.com/Archives/Archives2008.shtml
Henning Weddig
DK5LV
Am 20.05.2011 09:31, schrieb Nick:
> ( I am sorry about the message format.. I do not know whay this hapens.
> I am resending it hoping that it is better this time)
>
> Hi Ray and group,
>
> although I am not an expert on the Hybrid DDS/PLL subject, it just
> happened to study this design some months ago in order to understand the
> concept .
>
> I will try to pass my understanding on the programming part , which
> comes directly form the way (I understood) the design works.
>
> Besides the DDS, you also need a PLL chip. The PLL chip I assume it
> contains a phase detector, a reference frequency divider (usually called
> R counter) and a VFO frequency divider (usually called as N counter).
> Both counters are loaded with an integer divider (e.g 20 or 345 etc ).
>
> The PLL will lock if the VFO frequency divided by the N counter, matches
> the reference frequency divided by
> the R counter. As the reference frequency we use the output of the DDS.
> So, for example, if your VFO needs to cover the range 23-23.5 Mhz in
> steps of 10 hz , then one solution is the following (This is an
> example, and not the only or best solution )
>
> First, if your DDS chip is clocked at 400Mhz, with a 32bit tuning word
> it means that the minimum frequency is can generate is Fclock/(2^32)
> which is something around 0.0931 Hz.The output frequency of the DDS is
> Fo = TuningWord * (Fclock/(2^32)) (this is valid if your tuning word
> stays below 2^31). Thus the tuning word for a given frequency is
> TuningWord = (Fdesired * (2^32)) / Fclock
>
> Next, lets say that you divide the VFO by 230, so at 23 Mhz the divided
> VFO frequency becomes 100
> Khz. (this is the "step" of the PLL, see below) In order for the PLL to
> lock , your DDS along with any division selected by the value of the PLL
> R counter should result in a frequency of 100Khz. Let's say that you
> select R counter to be 10. This means that you need the DDS to produce a
> frequency of 1 Mhz. (do the math to find the DDS tuning word).
>
> If you need to move your VFO frequency to 23.000010 MHz , then you have
> to alter the frequncy of the DDS only. By how much? the VFO of 23.000010
> MHz is divided by 230 (N counter) which gives 100000.043478261 Hz . If
> you multiply this by the R counter (10) you need from the DDS a
> frequency of 1000000.43478261 Hz ...do the math to obtain the new tuning
> word. This goes on until the VFO reaches the frequency of 23.099999
> MHz. The DDS frequency at this point will be 1004347.7826087 Khz. when
> you reach 23.100000 MHz you need to set the N counter to 231. You
> should leave the R counter to
> 10. This means that the VFO of 23.100000 MHz is divided down to 100 Khz
> again, so the DDS has to start over again from 1 Mhz.
>
> In the above example this means that the PLL gives the coarse tuning in
> segments of 100Khz and the DDS does the fine tuning by generating the
> intermediate frequencies. The DDS should produce frequencies between 1
> Mhz and 1.0043477826087 Mhz. so you cover the required frequency range
> like this:
> R is set to 10,
> N=230, DDS 1...1.0043477826087 Mhz => VFO 23.0-23.099999 Mhz
> N=231, DDS 1...1.0043477826087 Mhz => VFO 23.1-23.199999 Mhz
> N=232, DDS 1...1.0043477826087 Mhz => VFO 23.2-23.299999 Mhz
> N=233, DDS 1...1.0043477826087 Mhz => VFO 23.3-23.399999 Mhz
> N=234, DDS 1...1.0043477826087 Mhz => VFO 23.4-23.499999 Mhz
>
> The DDS frequency should always be (VFO/N) * R in order to get a PLL
> lock. Now that you have the values of R, N and DDS tuning word, you have
> to consult the chipsets'
> datasheet in order to program each one of them with the appropriate
> sequence of bytes.
>
> You also have to take into account a number of factors like:
> a) the above calculations are performed with full precision but the DDS
> uses integer only values, which means that the rounding of the tuning
> word to the nearest integer value may result in a small frequency error
> b) The exact frequnecies combination (which affects the choice of N and
> R counter ) as well as the desicion of whether the PLL step should be
> 100Khz or 10Khz or 1Mhz belongs to the domain of PLL design
> c) You have to check which is the best DDS frequency range to use to
> minimize the DDS spurs (you ahould carefully read the chipset datashhet
> and you can also use the online tool from Analog Devices
> http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx) .
> You should generally stick below Fclock/3 and select a region that does
> not contain a lot of spurs or
> images.
>
> I hope this helps you to understand the part of managing the DDS and PLL
> counters. As far as the PLL design specifics are concerned, I am afraid
> I am not the right pers6345 2011-05-20 08:33:22 kb1gmx Re: DDS driven PLL 6347 2011-05-20 12:52:11 rcbuckiii Re: DDS driven PLL 6348 2011-05-20 13:19:11 rcbuckiii Re: DDS driven PLL 6349 2011-05-21 13:31:27 kb1gmx Re: DDS driven PLL