EMRFD Message Archive 4949

Message Date From Subject
4949 2010-08-29 16:29:15 Ashhar Farhan Using a DDS as a PLL reference
Consider a simple PLL running at about 50 MHz with a fixed divider N=100
that is fed to a phase-frequency detector running nominally at 500 KHz . The
reference to this phase-frequency detector is from a DDS. Hence to tune the
PLL to a different frequency we just change the DDS frequency.

Now, we are faced with a dilemma here, we can increase the reference
frequency to 5 MHz for better PLL performance, but this will increase the
quantization noise (and hence increase the spurs) in the DDS (assuming that
the DDS' clock frequency cannot be altered).

Hence, what is a good compromised? Will the performance be better if the PLL
is run at a higher reference frequency or is the DDS performance more
desirable with lower ref freq?

- farhan VU2ESE


[Non-text portions of this message have been removed]
4955 2010-08-30 06:02:22 kb1gmx Re: Using a DDS as a PLL reference
4956 2010-08-30 07:15:44 joop_l Re: Using a DDS as a PLL reference
How wide does the 5MHz frequency need to be? If it is narrow you can pass it via a crystal filter. For a bit wider you could probably use a ceramic resonator. A lot of the spurious will be reduced.
4958 2010-08-30 09:54:43 Johan H. Bodin Re: Using a DDS as a PLL reference
joop_l wrote:
> How wide does the 5MHz frequency need to be? If it is narrow you can pass it via a crystal filter. For a bit wider you could probably use a ceramic resonator. A lot of the spurious will be reduced.

Joop, you took the words out of my mouth :-)

I was just about to write this when your message arrived. I remember an article
(QST? QEX?) written by Ulrich Rohde which described such a hybrid synth' using a
crystal filter between the DDS and the PLL reference input. Fine tuning was made
with the DDS and the coarse steps by the PLL divider.

73
Johan SM6LKM
4959 2010-08-30 13:28:04 joop_l Re: Using a DDS as a PLL reference
Right, something like this probably:
http://www.thegleam.com/ke5fx/synth.html

Joop
4960 2010-08-30 14:30:35 kb1gmx Re: Using a DDS as a PLL reference
4961 2010-08-30 15:50:43 joop_l Re: Using a DDS as a PLL reference
I am not sure if I understand what you mean. There are some random spur search files
4962 2010-08-30 20:49:04 kb1gmx Re: Using a DDS as a PLL reference
Joop,

The spurs have to be of enough amplitude to drive digital logic
typically used as phase detector. If their amplitude is more than
40db down how can that happen if the main desired signal has
enough over drive to saturate a sine to square converter?

Conversely if the Spurs are both that close in and less than
20db down that DDS is especially poor and maybe not used
at all.

It's very important to reflect on what the phase comparator sees
and how it reacts. Digital ones do not, analog ones may. Then we have to looks at the loop filter where the error voltage is dealt with or we would have the error directly modulating the VCO
and reflecting system noises as FM modulation.

I've also done this using a DDS that didn't use a digital word to sine converter and used the high order bit as a square wave source
and found it to be a good way to clock a phase comparator cleanly.
It always struck me odd that in tracking and scaling PLL systems
referenced to DDS based hardware that the whole sine table and
digital to analog was done when it's both excess and the source of the spurs.

The article used a DDS that was maybe state of the art in 2001
(article published in 2003)but would not pass muster for current parts. Also the PLL was using fractional /N counters where the amounts of jitter can be higher. Followed by a Loop filter with
less than a few hundred Khz. and the target output was for the 1ghz
to 2ghz band where the /n was much larger. That system looked to have a reference of about 2mhz making the /n about 500-1000.
that makes the PLL a tracking multiplier and any bad habits of
the reference are going to be multiplied.

Farhan as I read it is shooting for 50mhz and can use parts
that are much better and have fewer close in spurs below 20mhz
as a far cleaner starting point and less multiplication.

Being as I've built tracking and second order PLLs and a few hybrids for my 6M radios it's not nearly the problems that a 1500mhz radio
would have.


Allison




4963 2010-08-30 23:09:55 Ashhar Farhan Re: Using a DDS as a PLL reference
joop, johan, allison and others,

i think i should explain my dilemma better. i am not using a standard dds
chip. instead, i am using a pic (16F628).
this chip simulate a DDS at appox. 1 MHz clock frequency with 24 bit
accumulator and 8 bits in the output.

My question is: what is a good frequency to run this at? If i try generating
a 200 KHz frequency, there will be 4 to 5 samples in every time period, they
will appear to be 'modulated' due to the quantization noise. however, as i
keep decreasing the output frequency, the waveform gets better and better.

so, the question is really, how far away should the output frequency be from
the clock frequency? I plan to filter the output of the dds through an
active filter before applying to the phase-frequency detector (the standard
two D-flip flop configuration).

- farhan

4972 2010-08-31 13:48:59 victor Re: Using a DDS as a PLL reference
Alison you have one error. If we have at the DDS output a carrier with a spur at 40dB below the carrier, when you pass them through a sine to square converter (a limiter or a comparator) you still will have spurs at the square wave output, and this is because the limiter eliminates the AM modulation but not the phase modulation. So at the limiter output you will get the wanted carrier with TWO spurs, one at the original spur location and the other at the other side of the wanted carrier. Their level will be only 6dB lower than the original spur at the input. This spurs, if their separati
4975 2010-08-31 17:17:13 kb1gmx Re: Using a DDS as a PLL reference
4977 2010-08-31 18:22:10 kb1gmx Re: Using a DDS as a PLL reference
4981 2010-09-01 00:51:11 hanssummers2000 Re: Using a DDS as a PLL reference
Hi Alison

> > Alison you have one error. If we have at the DDS output a carrier with a spur at 40dB below the carrier, when you pass them through a sine to square converter (a limiter or a comparator) you still will have spurs at the square wave output, and this is because the limiter eliminates the AM modulation but not the phase modulation. So at the limiter output you will get the wanted carrier with TWO spurs, one at the original spur location and the other at the other side of the wanted carrier. Their level will be only 6dB lower than the original spur at the input. This spurs, if their separation from the carrier is less than the PLL loop bandwidth, will be present also at the PLL output, just as any PLL reference signal phase noise. Their level will be increased as the PLL "N" divider increases, so if the PLL output is at 1GHz these spurs at PLL output will be much higher than if the PLL output is at 50MHz.
> > Victor - 4Z4ME
>
> Correct _if_ the gain is sufficient to respond to the spur. The usual
> sine to square is a bipolar transistor so it's possible to never see the spur do to lack of level. The solution is to avoid more gain than needed in the sine to square process. After all a reasonable DDS has spurs that typically are better than 40db (more like 50-60db) down so we can make them invisible by establishing threshold. Seems to me if the desired is 1V and the spur is less than .01V it's easy to ignore the spur even if the threshold is 0.2V.

I don't think this is correct.

My understanding: the sine-to-square, or threshold comparator, operates in the time domain, not in the frequency domain. At any instant in time its output just depends on whether the input threshold is breached or not. It just sees a voltage at its input, it doesn't know anything about whether that voltage contains a contribution 60dB down spur, or not.

For example, if your wanted signal is 50MHz. Say you have an unwanted spur, 80dB down, at 51MHz. The actual sinewave present at the squarer input, is 50MHz but will be slightly distorted by the additive presence of the small 51MHz component. What this means for the level threshold, is that it the level will be breached slightly earlier or later than would have been the case if it were not there. The edges of the squarewave output will be shifted slightly, earlier or later. This 51Mhz spur therefore shows up in the output as jitter.

It doesn't matter if your squarer gain is 10dB and your unwanted spur is 100dB down. You will STILL get jitter in your squarewave output, from that 100dB down spur. Call it jitter, call it phase noise, call it FM noise, whatever you like. By the time it gets through to the loudspeaker of your radio, it's simple unwanted noise on your audio.

> A filter is nice, if the spur is well defined, high in amplitude and stays outside the needed range but when you move a DDS the spurs move and do not maintain the same spacing or relationships for level.
>
> Also the spur is not FM, it's multiple signals within the bandwidth
> and the worst case is they could cause a system to lock on the spur of develop significant phase jitter (FM noise). But only if the spur is great enough to be a clock edge to the phase detector.

I don't think so, see above.

> My preference is to no use sine wave output DDS. You can skip the
> sine and D to A and get a perfect square wave with only the jitter from logic propagation and clock. In most of the sine output DDSs
> that is where the spurs come from, lack of bits in the since table
> and D to A with distortion or lack of resolution.

I don't agree with that either. If you are trying to create a 157MHz output squarewave, and you have a 1GHz system clock, and you imagine only toggling your (DDS) output pin either on or off, then you can't get a perfect number of 1GHz clock cycles into each wanted output 157MHz clock cycle. You approximate. You end up with jitter on the 157MHz output which is unavaoidable.

It doesn't make any difference whether the output is a square wave with jitter, or has been put through a D-A converter and is a sinewave with distortion. The end result is exactly the same: spurs. If you look at this imagined 157MHz square wave on a spectrum analyser you'll still see the spurs just the same (PLUS, all the harmonics of course). So ehter you are sine or square, the same problems produce the same end result: spurs.

73 Hans G0UPL
http://www.hanssummers.com
4982 2010-09-01 03:39:25 victor Re: Using a DDS as a PLL reference
Hans,
Thanks for your response. I couldn't phrase it better.
By the way I am an admirer of your work in your web site.
Very nice to see you are active here too.
Victor - 4Z4ME

4983 2010-09-01 08:21:32 kb1gmx Re: Using a DDS as a PLL reference
4984 2010-09-01 10:09:12 Lasse Moell Re: Using a DDS as a PLL reference
For those who want some design hints and how to calculate spurs, the
old Qualcomm application note can be found at the end of this document
(section 9)!
http://www.sss-mag.com/pdf/synthbk.pdf

Enjoy the reading!!

/Lasse SM5GLC
4985 2010-09-01 10:12:14 victor Re: Using a DDS as a PLL reference
Allison,
Your explanation of the DDS output signal is close to reality when the output signal frequency is much much lower than the Clock frequency. If the output signal frequency is not a small fraction of the Clock then the phase accumulator will have large phase jumps at each step and the output signal will not resemble at all the signal needed. In frequency domain you will see many aliasing signals at large amplitude. if you don't use a low pass filter to reject them and you will still connect this signal to a digital limiter, then you will have a very messy signal.
About phase noise of the DDS itself of course it is relative to the DDS Clock phase noise and its very low. What we meant about the Sine signal + Spur is that the spur can be thought as a phase modulating the carrier when it passes through the limiter.
Yes, many years ago I did the experiment of connecting two sine signal one large and one weak to a limiter and the limiter output spectrum was exactly as predicted: two spurs at both sides of the carrier, attenuated by 6 dB relative to the spur level at the limiter input (relative to the carrier - dBc).
You talk about the limiter threshold and that the spur is smaller than that threshold and so it does not appear at the limiter output. The error is that at the DDS output (limiter input), the two Sine signal exist all the time and if you make a sum of these two sine signal instantaneously at each time point, you will see that the spur signal distorts slightly the nice waveform of the large signal, so the spur affects the summed signal at ALL the time points, so there is no meaningful importance for a threshold of the limiter. Any digital gate senses only when the input signal crosses its switching threshold and the exact time that that happens is certainly influenced by the spur, this means that the spur modulates the large signal by phase modulati
4986 2010-09-01 13:23:04 hanssummers2000 Re: Using a DDS as a PLL reference
Hi Victor,

Nice to know you have actually performed such an experiment. It's always nice when the experiment lines up nicely with the theory.

Here at G0UPL HQ the equipment is poor indeed, and definitely not up to such measurements. I have a Racal 9911 frequency counter, an old Heathkit frequency counter (nixie tube readout), a Motorola 2001D communications analyser, an HP1741A analogue storage 100Mhz 'scope. All of that must be at least 25 years old or more. Anything newer, is homebrew and so far, not as sophisticated (0-140MHz spectrum analyser, various frequency counters, etc.).

73 Hans G0UPL
http://www.hanssummers.com



4987 2010-09-01 13:43:57 kb1gmx Re: Using a DDS as a PLL reference
4988 2010-09-01 14:03:28 victor Re: Using a DDS as a PLL reference
Hans,
I have done that at my workplace many years ago. We wanted to know how a switching mixer (a passive diode double balanced mixer) behaves when the LO is the sum of large sine signal summed with with a much lower level spur, and it compared well with injecting the same composite signal into a comparator that squared the signal.
Doing that in the place that I worked then was very easy using two Marconi 2018 generators to generate the signal and a spectrum analyzer to analyze the output signal.
For the mixer test a third Marconi 2018 was used to inject the RF signal to the mixer input. In this test the result was that the spur appeared at the IF port of the mixer at both sides of the converted signal and its level was 6dB lower (in dBc - below the carrier!) than it was in the LO port.

Victor - 4Z4ME

4989 2010-09-01 14:36:40 victor Re: Using a DDS as a PLL reference
Allison,
I finish my comments
4990 2010-09-01 14:48:12 kb1gmx Re: Using a DDS as a PLL reference
4991 2010-09-01 14:49:59 kb1gmx Re: Using a DDS as a PLL reference
4992 2010-09-01 15:30:02 kb1gmx Re: Using a DDS as a PLL reference
4994 2010-09-01 17:12:51 victor Re: Using a DDS as a PLL reference
Allison,
In one of my earlier posts I remarked that spurs at the Reference clock of a PLL will appear at the PLL output if the frequency difference between the reference clock and the spur is lower than the bandwidth of the PLL loop (what you call integration time of the PLL loop filter). In your example the digital mixer output will contain signals whose frequencies will be the difference and sum of the harmonics of the input frequencies. In this case it seems that the 6th harmonic of the 7MHz and the 43MHz will give an output at 1MHz. if the rest of the mixer output signals are at higher frequency, than the PLL will filter them and they will not have influence
4995 2010-09-01 17:37:49 victor Re: Using a DDS as a PLL reference
Allison,
It seems you do not know what dBc means.
dBc means dB down from the carrier. So if we take the mixer example, if the LO power is +10dBm, summed with a spur 1kHz above the LO frequency with a power of -30dBm, we have here a one-sided spur at -40dBc.
If we connect a single -30dBm signal to the mixer input, we will get an IF signal of -36dBm (assuming 6dB mixer loss). The IF signal will have two spurs, one above and one below the main IF signal (at 1khz intervals) with the level of -82dBm or in other words -46dBc.
The spur at the LO port modulated the input signal, the spur level at the output has nothing to do with the mixer insertion loss. the insertion loss affected only the input signal at the R port.
Leaving mixers behind, how do you explain this phenomena when we input a 5dBm signal summed with a spur of -40dBm (which is then -45dBc) and connect it to a comparator (or digital gate). At the output we get a main signal at a power that depends on the device used, so lets say the main signal power at the output is 10dBm, What will be the power of the two spurs (above and below the main signal frequency):-41dBm or in other words -51dBc. No 6dB conversion loss here, so?
About giving a graphic phasor explanation I might do that later
4996 2010-09-01 19:28:32 kb1gmx Re: Using a DDS as a PLL reference
4997 2010-09-01 19:39:19 k5nwa Re: Using a DDS as a PLL reference
At 09:28 PM 9/1/2010, you wrote:
>
>
>If the gate/transistor is saturated I cannot see how the signal even
>passes. The 40dbm signal is well below threshold. That suggest
>either not saturated or incidental bias and mixing. If the signal
>is there it possible there is incidental gain due to bias.
>

You are assuming that the signals have zero rise time, but in reality
they don't so there can be uncertainty , the point at which you go
from a zero to a one or the reverse must remain constant.

Since these two signals are at two frequencies their phase
relationship keeps changing, that noise spur occurring near the
switching point of the main signal could precipitate the output to
switch a little earlier or sometimes a little later, that is called
jitter, and it translates to phase noise.


Cecil
k5nwa
< www.softrockradio.org > < www.qrpradio.com >
< http://parts.softrockradio.org/ >

Never take life seriously. Nobody gets out alive anyway.
4998 2010-09-01 20:20:16 victor Re: Using a DDS as a PLL reference
Allison,
Read my comments in the text.

4999 2010-09-02 05:42:03 joop_l Re: Using a DDS as a PLL reference
> > Leaving mixers behind, how do you explain this phenomena when we input a 5dBm signal summed with a spur of -40dBm (which is then -45dBc) and connect it to a comparator (or digital gate). At the output we get a main signal at a power that depends on the device used, so lets say the main signal power at the output is 10dBm, What will be the power of the two spurs (above and below the main signal frequency):-41dBm or in other words -51dBc. No 6dB conversion loss here, so?
>
> We should as most are amplitude sensitive and that doe complicate
> tracking or multiplying PLL systems.
>
> If the gate/transistor is saturated I cannot see how the signal even passes. The 40dbm signal is well below threshold. That suggest either not saturated or incidental bias and mixing. If the signal
> is there it possible there is incidental gain due to bias.
>

The act of putting a comparator in the path does not remove spurs. Imagine that the spur would be equal in size to the desired signal. Which one would be present in the output, the signal or the spur or both? Both of course.
It can be understood that spurs further down in power will show up less in the digital output. But you have not shown that there is a proportional bigger decline in spur contribution with lower spur level on the input. For now I assume the spur contribution on the comparator output is as many dBc as it is on the input.

Joop
5000 2010-09-02 11:06:54 ehydra Re: Using a DDS as a PLL reference
kb1gmx schrieb:

> [..]
>
> This is a system level example. It has arguably multiple time varying signals all with levels near the center frequency level
> due to IF limiting. In short a very narrow filter.
>

There are several papers available discussing the effects of additive
noise (amplitude and LO phase noise) in the field of BPSK systems. For
example how effective is receive hard-clipping with a comparator in
deep-space communications. This is very similar!

And I tested several ideas how mixer and comparators work just by
running them thru LTspice with pseudo-noise as a lengthy simulation
analyzed at in and out with FFT.

regards -
Henry


--
ehydra.dyndns.info
5001 2010-09-02 11:12:48 ehydra Re: Using a DDS as a PLL reference
victor schrieb:

> Its' impact is if the filter is wider than the spur (1khz) its
> reproduced. If the filter is narrower its attenuated by the
> character of the filter and any divider chain. Since we know people
> have designed PLLs with 1khz
>> references (and lower) it's possible to filter it acceptably

I would like to add that a divider chain is PLL analytical a low-pass
filter, because it integrates the time-domain signal at the input. See
the classical 74297. Look in the TI AppNotes.


- Henry


--
ehydra.dyndns.info
5002 2010-09-02 11:16:15 ehydra Re: Using a DDS as a PLL reference
joop_l schrieb:

> The act of putting a comparator in the path does not remove spurs.
> Imagine that the spur would be equal in size to the desired signal.
> Which one would be present in the output, the signal or the spur or
> both? Both of course. It can be understood that spurs further down in
> power will show up less in the digital output. But you have not shown
> that there is a proportional bigger decline in spur contribution with
> lower spur level on the input. For now I assume the spur contribution
> on the comparator output is as many dBc as it is on the input.
>

I think this is not true. The spur suppression is not linear but depends
on the relative level of the useful carrier signal too.

But at the moment I don't have a reference for this.
Try it with LTspice with a transistor-level comparator to see the true
behaviour.

- Henry


--
ehydra.dyndns.info
5003 2010-09-02 14:02:39 kb1gmx Re: Using a DDS as a PLL reference
5004 2010-09-02 14:08:33 kb1gmx Re: Using a DDS as a PLL reference
5005 2010-09-02 14:12:00 kb1gmx Re: Using a DDS as a PLL reference
5006 2010-09-02 15:13:57 kb1gmx Re: Using a DDS as a PLL reference
5007 2010-09-02 15:30:23 Johan H. Bodin Re: Using a DDS as a PLL reference
Why bother with PLLs and mixers when you can make a pretty good and extremely
clean receiver with six or maybe seven chips? (not counting the chips in the PC...)

https://sites.google.com/site/sm6lkm/lo-noise

To be honest, even though the Perseus represents the state of the art, I still
enjoy playing with SDR (Solder Defined Radio - an expression invented by Alberto
I2PHD less than 24 hours ago). ;-)

73
Johan SM6LKM
5008 2010-09-02 16:37:50 joop_l Re: Using a DDS as a PLL reference
I just ran a simulation in LT-SPICE. It used the LT1015 as comparator with two voltages sources in series at the input. One is 100Hz at 1V. The other 101Hz at 100mV, 10mV and 1mV. It ran for 13 seconds.
So the other is -20, -40 and -60dBc.

On the output I see several mixing products, but there are two major spurs at 99 and 101Hz. Each of them are at respectively about:
-26, -46 and -66dBc.

Right now I have no reas
5009 2010-09-02 16:54:46 victor Re: Using a DDS as a PLL reference
Allison, what do you say about these results? its exactly as I said it should be.
Victor - 4Z4ME

5010 2010-09-02 17:00:17 victor Re: Using a DDS as a PLL reference
5011 2010-09-02 18:48:53 kb1gmx Re: Using a DDS as a PLL reference
5012 2010-09-02 19:03:20 kb1gmx Re: Using a DDS as a PLL reference
5013 2010-09-02 19:15:14 kb1gmx Re: Using a DDS as a PLL reference
5014 2010-09-02 19:41:39 kb1gmx Re: Using a DDS as a PLL reference
5015 2010-09-03 00:35:15 victor Re: Using a DDS as a PLL reference
Sorry allison, didn't mean to sound abusive. Only I was saying that the simulati
5016 2010-09-03 00:52:54 victor Re: Using a DDS as a PLL reference
In my previous post I stated that the comparator (or switching mixer) output phase peak jitter is +/-ArcTan(A/B). Now, you don't see the sundry matrix of multiples and their sums and differences as you expected to see just because the phase modulation index is very small (because of the large amplitude difference of the two sine signals). The additional output spur carriers are so weak and are below noise level. I guess that if the simulati
5017 2010-09-03 05:31:00 kb1gmx Re: Using a DDS as a PLL reference
It's already many postings old. For those that are not deeply steep in theory or haven't applied it in years some of the comments are
so obscure as in "Doesn't every one know that?". I know that
is not true.

To use that quantization you have to do further math..

What did you say about the other two thirds of the posting?
I will skip over the identity case for a DBM to the one that
seemed upsetting. So I repeat..

---------------next case-------------------------------

IF I take both of those tones combine them with a hybrid and
apply them to any _ONE_ port I expect trash to emerge and in
larger quantities then would seem reasonable from the remaining
ports.

Do we have a problem here? Why do you think applying that combined signal to the L port will not make it all (a few DB down) appear at the I port? Why is balance or "B" not an answer?

You say it did and I said no surprise. There is no dispute we
agree. Why does the DBM exhibit that behavior?

This is for the benefit of the other readers here, you did an experiment but never explained the behavior. and for all that
use DBMs it's important.


Allison

5018 2010-09-03 05:38:38 kb1gmx Re: Using a DDS as a PLL reference
I already knew that any non linear device/system will mix the
signal and result in other behaviors. I was being methodically
dense to get the reason why stated. It never was. just a lot of
"but it's there and the experiments prove it.". There was no
why or how. One person posted the answer, simply and understandably.

If we want people to understand or at least approach more complex electronics then behaviors of why a spur is important have to be explained with more than a "it does that" or see obscure and difficult reference.


Allison


5020 2010-09-03 08:32:26 victor Re: Using a DDS as a PLL reference
Allison,
Well, I tried for a moment not to be lazy and I wrote down my little explanation for my simulati
5021 2010-09-03 08:37:02 ehydra Re: Using a DDS as a PLL reference
Victor! I would it welcome if you avoid the full-quote of text.

Thanks -
Henry

--
ehydra.dyndns.info
5024 2010-09-03 08:48:52 victor Re: Using a DDS as a PLL reference
Henry,
Sorry for being dumb here, what do you mean? Erasing the previous messages from the new reply?
Is there an automatic way to do this?
Victor - 4Z4ME

5030 2010-09-03 15:30:50 ehydra Re: Using a DDS as a PLL reference
Hi Victor -

I don't know about an automatic way. So I clear it by hand leaving
important references alone.

I noticed that some messages are 25KB here
5031 2010-09-03 15:48:08 ehydra Re: Using a DDS as a PLL reference
BTW: I rumbled (by analyzing [I think] good designs) about that using
prime numbers for divider values or at least using divider values with a
big as possible prime number content will give the least spurs content.

I think this is especially important if one uses a single reference
oscillator for the whole transceiver. So IF is a sub-multiple of the
input frequency! I think this will give the least phase-noise and and a
way to the most sensitive receiver. Otherwise multiples of the IF
frequency can leak into the input of the RF stage.

So tried to google about that but found nothing really useful. May be
because I'm not a native english speaker?? Or is it handed as a
trade-secret?

Does somebody know good papers about that?


regards -
Henry


--
ehydra.dyndns.info


kb1gmx schrieb:
> I already knew that any non linear device/system will mix the signal
> and result in other behaviors. I was being methodically dense to get
> the reason why stated. It never was. just a lot of "but it's there
> and the experiments prove it.". There was no why or how. One person
> posted the answer, simply and understandably.
>
> If we want people to understand or at least approach more complex
> electronics then behaviors of why a spur is important have to be
> explained with more than a "it does that" or see obscure and
> difficult reference.
5033 2010-09-03 16:21:16 kb1gmx Re: Using a DDS as a PLL reference
5035 2010-09-03 17:44:07 ehydra Re: Using a DDS as a PLL reference
kb1gmx schrieb:
>> Does somebody know good papers about that?
>
> Starting in the EMRFD and pull references from there. There are many.
>

I'm mainly focused for the prime number discussion. But thanks for your
more general infos!

The problem with lower HF is that Amateurs like to have wide-band
antennas. The antenna ist the best amplifier _and_ filter!

To be practical: I made a transceiver with a PC clock generator chip
where later in the design process I found, that the clock dividers are
too short for the very low IF I used. So I needed multiples of the IF
fitting two divider chains simultaneously. After experimenting with
values and some analytic mathematics I finally found candidates and a
generic pattern of usable frequencies. Before that it driven me just
crazy recognizing that maybe the clock chip will not work because the
dividers are too short... (but the rest of the design was almost
completed and fixed).
Ok, it runs very fine. I like it. I know that the internal PLL-LO in
those chips cannot reach the quality of external VCOs. But it is cheap
and very small (and exotic ;-)!
Later on I took the road to analyze the divider values with prime numbers...

- Henry

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ehydra.dyndns.info
5036 2010-09-03 19:45:27 kb1gmx Re: Using a DDS as a PLL reference
5041 2010-09-04 06:01:23 victor Re: Using a DDS as a PLL reference
Henry,
I dont see the connection between the IF frequency value and the PLL divider.
The PLL (simple single loop PLL) reference frequency value is equal to the PLL frequency step. If we want a LO with 25kHz output signal steps, you use a PLL reference frequency of 25kHz. The PLL output frequency is equal to receive frequency added to the IF value (for high side LO mixing). All these values are not related, so you just put them in and just get the divider N value: (Frx+Fif)/Fref .
I don't see how this or other N value can influence
5067 2010-09-07 14:05:08 ehydra Re: Using a DDS as a PLL reference
Hi Victor -

I don't mixed it with other architectures. It is a simple integer-N PLL.
Yes, the most important spurs are located delta IF around the carrier.

But I forgot to mention that the particular system works with a very low
IF filtered with a SCF. After that filter the radio data signal is
demodulated with a digital demodulator. This SCF and the demod are
clocked by the same TCXO source as the PLL reference clock.

Even the microcontroller is clocked by a subharmonic auf the TCXO.

So the whole system is phase-locked to ONE clock.


regards -
Henry

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ehydra.dyndns.info


victor schrieb:
> Henry,
> I dont see the connection between the IF frequency value and the PLL divider.
> The PLL (simple single loop PLL) reference frequency value is equal to the PLL frequency step. If we want a LO with 25kHz output signal steps, you use a PLL reference frequency of 25kHz. The PLL output frequency is equal to receive frequency added to the IF value (for high side LO mixing). All these values are not related, so you just put them in and just get the divider N value: (Frx+Fif)/Fref .
> I don't see how this or other N value can influence on PLL spurs.
> A good PLL almost don't have spurs (except harmonics of its output frequency). The only spurs that might be there is spurs around the output signal, distanced from it by the Fref value (25kHz at the above mentioned example).
> Maybe you mixed up something with Fractional-N divider in a Fractional-N PLL or something about the Spurs generated in DDS which has a sigma-delta mechanism that resembles the Fractional-N PLL with noise shaping. But this is totally another subject.
> Victor - 4Z4ME
>
5068 2010-09-07 15:06:20 victor Re: Using a DDS as a PLL reference
Hi Henry,
Sorry but I still can not see the connection between the value of the PLL N divider and spurs.
The only way that the reference clock could cause problems is by interference caused by radiation or bad PCB layout. In such a case, if the main clock that runs to multiple places on the PCB is square wave (50% duty cycle), it might be to some benefit if the PLL output frequency is at an even harmonic of the clock, because the even harmonics of a 50% duty cycle square wave are greatly attenuated in comparis