EMRFD Message Archive 10172

Message	Date	From	Subject
10172	2014-07-23 15:57:52	harizyacine	fet transistor
Hi,  please, can nFet transistor with  resistor connected to the drain only ( no source resistor)  and biasing resistor of the gate circuit Amplifies signal that comes to the gate for example RF and what it’s Gain ? Thank you
10216	2014-08-06 08:50:15	tttpppggg	Re: fet transistor
Yes, with a DC bias path between the drain and the gate bias circuit. That path can also give some negative feedback. This will be true of an enhancement mosfet, but for a jfet the gate must be negatively biased, so you would need to have a negative supply voltage in the gate bias circuit.  For the n channel jfet if that additional supply rail is not acceptable then you have to put in a source resistor to ground, which will develop the negative VGS when the gate is DC grounded.  Best of all would be to prototype the circuit at low frequency and observe your results. Then you will have some real footing rather than a bunch of paper. That is also the theme of this group. I think then you'll get more responses here too. This is a practice which requires action, and there are many ways to get there. You may wind up with your own style of prototype based on the tools you have to work with. Probably you should start with leaded parts on a solderless breadboard, but other options exist. You can work with RF up to 10 MHz this way, but it would be better to stay lower.
10236	2014-08-22 07:56:17	tttpppggg	Re: fet transistor
I have a correction. If you pick a loss IDSS jfet you can skip the bias resistor. There are numerous schematics with the 2n4416 in  the ARRL handbook with no bias resistor. Try this with a J310 and you'll likely burn it. Most of my experiments have been around the dual gate mosfet so I'm a bit out of it wrt jfets. Sorry about the bad info.